In the latest version of AIDA64, Preliminary info for AMD’s upcoming 7nm Zen 2 based, 3rd Gen Ryzen Threadripper ‘Castle Peak’ high-end desktop and EPYC Rome server processors has been added.
The company is expected to launch them at the Computex 2019, next month and AMD’s EPYC Rome processors based on the 7nm Zen 2 architecture are not far from launch.
Thanks to STH, we now know one key feature of the upcoming processor which would absolutely crush the competition, if true. The 7nm Zen 2-based high-end CPU is expected to debut by the second half of 2019 and will be a completely different beast compared to its predecessors. The release notes found on AIDA64 details quality-of-life improvements along with physical CPU information display for AMD Castle Peak, Rome, updated JEDEC memory module manufacturers database and more.
ServerTheHome has concluded that AMD’s EPYC Rome processors would feature a higher number of PCI Express lanes than anticipated. We know that a single EPYC Rome processor would rock 128 PCIe Gen 4 lanes but this is particularly the dual socket servers that we are talking about. AMD EPYC Rome Processors are expected to rock up to 162 PCIe Gen 4 Lanes, Possibly More which is twice the amount of Intel’s Flagship Xeon Platinum 9200.
Only the Intel 4S and 8P solutions can offer more lanes with the specific PCIe lane count for each server solution mentioned below :
- Xeon Platinum 9200: 2 CPUs with 40x PCIe Gen3 lanes each for 80 lanes total
- Xeon Scalable Mainstream: 2 CPUs with 48x PCIe Gen3 lanes each for 96 lanes total
- Xeon Scalable 4P: 4x CPUs with 48x PCIe Gen3 lanes each for 192 lanes total
- Xeon Scalable 8P: 8x CPUs with 48x PCIe Gen3 lanes each for 384 lanes total
AMD CPU Roadmap (2018-2020):
|Ryzen Family||Ryzen 1000 Series||Ryzen 2000 Series||Ryzen 3000 Series||Ryzen 4000 Series|
|Architecture||Zen (1)||Zen (1) / Zen+||Zen (2)||Zen (3)|
|Process Node||14nm||14nm / 12nm||7nm||7nm+|
|High-End Server (SP3)||EPYC ‘Naples’||EPYC ‘Naples’||EPYC ‘Rome’||EPYC ‘Milan’|
|Max Server Cores / Threads||32/64||32/64||64/128||TBD|
|High-End Desktop (TR4)||Ryzen Threadripper 1000 Series||Ryzen Threadripper 2000 Series||Ryzen Threadripper 3000 Series (Castle Peak)||Ryzen Threadripper 4000 Series|
|Max HEDT Cores / Threads||16/32||32/64||64/128?||TBD|
|Mainstream Desktop (AM4)||Ryzen 1000 Series (Summit Ridge)||Ryzen 2000 Series (Pinnacle Ridge)||Ryzen 3000 Series (Matisse)||Ryzen 4000 Series (Vermeer)|
|Max Mainstream Cores / Threads||8/16||8/16||16/32||TBD|
|Budget APU (AM4)||N/A||Ryzen 2000 Series (Raven Ridge)||Ryzen 3000 Series (Picasso) Zen+?||Ryzen 4000 Series (Renior)|
Another main feature of the new EPYC Rome processors includes the SCH (Integrated Server Controller Hub) which is mentioned as the standalone 14nm I/O die. In the previous processors, AMD had to share a lot of resources, including PCIe lanes by relying on low-speed 3rd party controllers.